MECVE103 CMOS Digital Design I M.Tech Model Question Paper : mgu.ac.in

Name of the College : Mahatma Gandhi University
Department : Communication Engineering
Subject Code/Name : MECVE 103/Cmos Digital Design I
Sem : I
Website : mgu.ac.in
Document Type : Model Question Paper

Download Model/Sample Question Paper : https://www.pdfquestion.in/uploads/mgu.ac.in/5063-MECVE%20103%20CMOS%20Digital%20Design-I.doc

CMOS Digital Design I Question Paper :

M. TECH Degree Examination :
Model Question Paper
Branch: Electronics &Communication Engg.

Related : MGU MECCE106-4 High Frequency Circuit Design M.Tech Model Question Paper : www.pdfquestion.in/5061.html

Specialization: VLSI & Embedded Systems
First Semester
MECVE 103 CMOS DIGITAL DESIGN I
(Regular-2013 Admissions)
Time: 3 hrs.
Maximum marks: 100
Answer all questions :
Each question carries 25 marks :
1. a) With neat sketches, explain the transfer characteristic of a CMOS inverter. (5)
b) Design an inverter using (i) NMOS; (ii) CMOS and (iii) pseudo NMOS. Compare and explain the characteristics of above designs. (8).

c) Sketch lay out of a 2-input NAND gate with transistor widths for equal rise and fall times.
Use Elmore delay model and compare the rising and falling delays in terms of R and C. If C=4 fF/µm and R=5 kO. µm in a 180 nm process, what will be the delay of a fanout of 3 NAND gates. (12)
OR

2. a) Explain on ratioed and non-ratioed inverters ? (5)
b) What is meant by logical effort. Discuss the logical effort of a 3 input, NAND and NOR gates (8)

c) With a suitable example, discuss how the logical effort can be effectively used to estimate the multi-stage delay of a logical network? (12)

3. a) Explain on various interconnect parasitic effects? (5)
b) Explain cross-talk and what are the techniques used to control the cross talk in interconnect wires? (8)

c) What is meant by a 3-segment pi model for the wire ? Consider a 2 mm long wire in a180 nm technology with a width of 0.32 µm. The sheet resistance is given as 0.05 O/ , and capacitance is 0.2 fF/ µm. Construct a 3-segment pi model for the wire? (12)
OR

4. a) What are the different interconnection capacitive components? (5)
b) Write a short note on inductive voltage fluctuation along the power lines? How this effect can be minimized in submicron technology? (8)

c) A 1 mm long wire in a130 nm technology is having a width of 0.32 µm. The sheet resistance is given as 0.05 O/ , and capacitance is 0.2 fF/ µm. Construct a 3-segment pi model for the wire? Also discuss on cross talk delay effects? (12)

5. a) Draw a dynamic 2- input NAND gate and explain the monotonicity problem while cascading two stages? (5)
b) Design a dynamic AND-OR-INVERT circuit, and comment on charge sharing issues in the circuit? (8)

c)Design a carry look ahead full adder with Multi Output Domino Logic? What are the advantages of NORA logic? (12)
OR

6. a) Draw the circuit of a dynamic 3-input NOR gate and explain its working? (5)
b) Design a BiCMOS 2-input NOR gate and comment on the output swing? (8)

c) What are the advantages of Silicon on Insulator (SOI) circuits? Explain the structure of an SOI inverter? (12)

7. a) Expalin different levels of abstraction followed in digital system design, using Gajski,s Y chart? (5)
b) Explain the types of Standard cell elements and Design of Standard Cell Library (8)
c) How Kernighan_Lin algorithm can be used for partitioning, Explain with a suitable example? (12)
OR

8. a) Design an Look UpTable(LUT) based full adder adder? (5)
b) Explain full custom design flow with the help of design flow chart. (8)

c) How Simulated Annealing as a probabilistic optimization technique, can be utilized in partitioning? Explain with the help of Boltzmann statistical function? Mention the analogy with thermal annealing. (12)

Syllabus :
Module 1 :
Static CMOS Inverter : DC Characteristics, Beta Ratio Effects, Noise Margin, Pass Transistor DC Characteristics. Delay Models: Introduction, Definitions, Timing Optimization, Transiet Response.

RC Delay Model : Effective Resistance, Gate and Diffusion Capacitance, Equivalent RC Circuits, Transient Response, Elmore Delay, Layout Dependence of Capcitance, Determining Effective Resistance.

Linear Delay Model : Logical Effort, Parasistic Delay, Delay in a Logic Gate, Drive, Extracting Logical Effort from Datasheets, Limitations to the Linear Delay Model.

Logical Effort of Paths: Delay in Multistage Logic Networks, Choosing the Best Number of Stages, Example, Limitations of Logical Effort, Iterative Solutions for Sizing.

Module 2 :
Interconnect effects and power analysis : Introduction, Wire Geometry, Intel Metal Stacks
Interconnect Modeling : Resistance, Capacitance, Inductance, Skin Effect, Temperature Dependence.