MECVE106-4 Modeling of Embedded Systems M.Tech Model Question Paper : mgu.ac.in

Name of the College : Mahatma Gandhi University
Department : Communication Engineering
Subject Code/Name : MECVE 106-4/Modeling of Embedded Systems
Sem : I
Website : mgu.ac.in
Document Type : Model Question Paper

Download Model/Sample Question Paper : https://www.pdfquestion.in/uploads/mgu.ac.in/5065-MECVE%20106_4%20Modeling%20Of%20Embedded%20Systems.doc

Modeling of Embedded Systems Question Paper :

M. Tech Degree Examination :
Model Question Paper :
Branch: Electronics &Communication Engg

Related : MGU MECVE105-4 Electronics System Design M.Tech Model Question Paper : www.pdfquestion.in/5064.html

Specialization: VLSI & Embedded Systems
First Semester :
MECVE 106-4/Modeling of Embedded Systems
(Regular-2013 Admissions)
Time: 3 hrs.
Maximum marks: 100
Answer all questions :
Each question carries 25 marks. :
1) a. Write a short note on Y chart (5)

b. Derive the equation for the theoretical upper bound on the speedup S that can be obtained in a sequential program when only a fraction P of the program can be accelerated (e.g. through implementation in custom hardware) by a maximum speedup factor of A (a speedup of A = 2 means fraction P can be run twice as fast).

What is S for P = 60% and A = 10? What is S for P = 60% and A = 8 (running the accelerated portion in zero time)? What is your interpretation of the results? (8)

c. During design space exploration as part of the system design process, the target system architecture and its key architectural parameters are decided on. These design decisions have a major influence on the final design quality metrics such as (i) performance, (ii) power, (iii) cost, and (iv) time-to-market:

(a) Briefly discuss how the following target platform styles rate in relation to each other in terms of the metrics listed above:
A pure software solution on a general-purpose processor
A general-purpose processor assisted by a custom hardware accelerator/co-processor
A general-purpose processor and a specialized processor (DSP or ASIP)

(b) Sketch a potential simple strategy for exploring the design space for a given application under a given set of constraints/requirements. (12)
OR

2) a. Differentiate FSMD and CDFG using examples (5)
b. Briefly outline the importance of specification model being free of implementation detail with respect to the top down design flow. Compare and contrast a top-down versus a bottom-up design methodology (8)

c. For the SDF graph shown in the figure
(i) Show that the graph is consistent and that it has a valid schedule
(ii) List all possible minimal periodic static schedules
(iii) Find the periodic schedule with the lowest token buffer usage. What is the minimum buffer usage. (12)

3) a. Explain earliest deadline first scheduling (5)
b. Explain in detail about the concept of code generation with C as target language. (8)
c. Explain in detail about automatic mapping with the help of GSM encoder application (12)
OR

4) a. With the help of diagram explain the embedded system software synthesis flow with TLM as input. (5)
b. Differentiate between RTOS based multitasking and interrupt based multitasking. (8)
c. For the given component table generate a platform mapping using the algorithm flow chart given in the fig for the application graph shown in the fig. (12)

5) a. Briefly explain hardware synthesis design flow. (5)
b. For the design given below draw and explain the

(i) FSMD model for functional unit chaining(ii) FSMD model for functional unit multi cycling (iii) data path with chained and multi cycle functional units. Square root approximation (SRA) of two signed integers a and b using the formulae va2 + b2 ˜ max((0.875x + 0.5y), x); where x = max(|a|, |b|) and y = min(|a|, |b|)?. (8)

c. Draw an FSMD model for the design mentioned in the previous question. Create a variable table, operation usage table and connectivity table for this FSMD. Implement register sharing on the FSMD model using graph partitioning algorithm (12)
OR

6) a. Explain TC scheduling with the help of a flow chart? (5)
b. Write short notes on (i) RTL architectures with an FSM controller (ii) RTL architectures with programmable controller. (8)
c. For the design mentioned in question 5(b) draw an CDFG and implement ASAP,ALAP and RC schedule (12)

7) a. What do you mean by verification by simulation? Draw and explain the block diagram of a typical event driven simulator? (5)
b. What are the different optimization techniques employed to improve the performance of simulation? Explain in detail. (8)

c. Explain in detail the design of an MP3 decoder on different heterogeneous platforms using the embedded system environment tool set. The specification of MP3 decoder is that each frame of the decoder should be decoded with in 26.12 milliseconds. The block diagram of the MP3 decoder is shown below (12)
OR

8) a. Explain logic equivalence checking? (5)
b. Write a short note on any two system level design tool examples (8)
c. Explain in detail system level verification? (12)