NIELIT Question Paper : A Level Course Computer System Architecture

Name of the Institute : National Institute of Electronics and Information Technology (nielit.gov.in)
Name of the Course : A Level Course
Subject Code/Name : M4.3R4/Computer System Architecture
Document Type : Old Question Paper
Location : India
Website : nielit.gov.in

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NIELIT Computer System Architecture Sample Paper

B1.4-R4:
PART ONE :
(Answer all the questions)

Related / Similar Question Paper :
Internet Technology and Web Design Question and Answer Pdf

January 2012

1. Each question below gives a multiple choice of answers. Choose the most appropriate one and enter in the “tear-off” answer sheet attached to the question paper, following instructions therein. (1×10)

1.1 The circuit given below is
A) Combinational
B) Sequential
C) Hybrid
D) Analog

1.2 Which one of the following is universal gate?
A) AND
B) OR
C) NOR
D) NOT

1.3 In negative logic level 1 of the digital circuit is indicated by
A) 15v
B) 10v
C) 5v
D) 1v

1.4 An arithmetic shift-right is equivalent to
A) multiplying the number by 2
B) dividing the number by 2
C) changing the sign of the number
D) reversing the number

1.6 The following K-map solves to
A A
B 1 0
B 1 0
A) A
B) B
C) A
D) B

1.7 RAM is
A) Read and Add Memory
B) Random Access Memory
C) Rapid Access Memory
D) Redirected Address Bus Memory

1.8 A Computer has 64K memory starting from 0000. What is the last address of the memory?
A) 0FFF
B) FFFF
C) FFF0
D) None of the above

1.9 The fetch cycle is
A) first part of instruction cycle
B) last part of instruction cycle
C) intermediate part of instruction cycle
D) none of the above

1.10 The dedicated processor used for data transfer is
A) CPU
B) DMA
C) ALU
D) None of the above

2. Each statement below is either TRUE or FALSE. Choose the most appropriate one and ENTER in the “tear-off” sheet attached to the question paper, following instructions therein. (1×10)
2.1 Offline device is connected to CPU.
2.4 The postfix form of the expression (A+B)*(C+D) is AB+CD+*.
2.5 A stack organised computer does not use zero address instruction.
2.6 Hardware implementation of BSA instruction is used for handling interrupts.

2.7 In memory mapped I/O the addresses of memory and peripheral devices share the same address space.
2.8 Same clock pulse is used for asynchronous devices.
2.9 A buffer is needed in serial to parallel transfer mode.
2.10 Assembly language is a high level language.

PART TWO :
(Answer any FOUR questions)
5. a) Draw logic diagram of 2×1 multiplexer. Using the block diagram of 2×1 multiplexer, give the design of 4×1 multiplexer.
b) Draw the logic diagram of J-K Flip flop and give its truth table and characteristic table. (8+7)

6. a) Explain the design of 4 bit binary down counter. Also, draw the diagram. Use T flip-flop.
b) Give addressing modes of a computer, which require access to the main memory. (8+7)
7. a) Use Booth’s algorithm to multiply binary equivalent of (11)10 and (-13)10. Use 8 bits for representing the numbers.

b) How many address lines and input, output data lines are needed for a memory unit of 64K X 8 (where 64K is the number of words and word length is 8 bits). (7+8)
8. a) Explain the working of DMA transfer mechanism.
b) Describe working of cache. (7+8)
9. a) What are the various addressing modes of 8086? Explain each mode briefly. b) Explain the four segment registers of 8086. (8+7)

July 2012

Part One : (Answer all the questions)
1. Each question below gives a multiple choice of answers. Choose the most appropriate one and enter in the “tear-off” answer sheet attached to the question paper, following instructions therein. (1×10)
1.1 A combinational circuit which performs arithmetic addition of three bits is called
A) Half–adder
B) Full–adder
C) Double–adder
D) None of the above

1.2 Storage capabilities are not provided in
A) ROM
B) RAM
C) Secondary Storage
D) None of the above

1.3 ASCII is a ________ code
A) 6 bit
B) 7 bit
C) 8 bit
D) None of the above

1.4 The transfer of information from a memory word to the outside environment is called
A) Read operation
B) Write operation
C) No operation
D) None of the above

1.5 One bit in the instruction code may be used to
A) Distinguish between direct address and immediate address
B) Distinguish between indirect address and immediate address
C) Distinguish between direct address and indirect address
D) None of the above

2. Each statement below is either TRUE or FALSE. Choose the most appropriate one and ENTER in the “tear-off” sheet attached to the question paper, following instructions therein. (1×10)
2.1 Each combination of the variables in truth table is called minterm.
2.2 A decoder is a combinational circuit which converts binary information from n coded inputs to exactly 2n unique output.
2.3 Addition of a positive number and a negative number may result overflow.
2.4 The input register INPR and output register OUTR communicate with communication interface serially and with accumulator AC in parallel..
2.5 PUSH and ADD are examples of Zero – Address Instruction.
2.6 Booth Multiplication algorithm uses binary integer in signed 2’s complementation form.
2.7 For handling Divide Overflow condition, additional flip flop is needed.
2.8 Each peripheral device has associated with it an interface unit.
2.9 Cache memory is placed between main memory and secondary memory.
2.10 Both segments register DS and ES point to the address of data.