M.Tech VLSI Design Model Question Paper : ksoukarnataka.com

College : Karnataka State Open University
Degree : M.Tech
Year : II
Semester : 4th Sem
Stream : Computer
Subject : VLSI Design
Document type : Model Question Paper
Website : ksoukarnataka.com

Download Model/ Sample Question Papers :
Verilog Hardware : https://www.pdfquestion.in/uploads/6141-VERILOG.docx
Digital VLSI : https://www.pdfquestion.in/uploads/6141-DIGITALVLSI.docx
Embedded System : https://www.pdfquestion.in/uploads/6141-EMBEDDED.docx

VLSI Design Model Question Paper :

M.Tech : IV Semester
SPE :(VLSI Design)

Related : Karnataka State Open University M.Tech Multi Media Model Question Paper : www.pdfquestion.in/6142.html

Verilog Hardware Description Language :
Time : 3 Hours
Max. Marks : 75

INSTRUCTIONS:
** Question paper is divided into three groups.
** Each group is of 25 marks.
** Figure to the right in bracket indicates mark.
** Assume suitable data if necessary.

Group A : Answer any three questions. (Question No. 1 is compulsory)
Q.1 Explain ports with types. (05)
Q.2 What are the file input output functions? (10)
Q.3. What do you mean by operator? (10)
Q.4. Explain combinatorial UDP along with one example (10)
Q.5. Explain laxical conventions. (10)

Group B : Answer any three questions. (Question No. 6 is compulsory)
Q.6 Explain identifiers with example. (05)
Q.7 What is String and Multi dimensional array? (10)
Q 8. Explain parameterized modules along with one example. (10)
Q 9. Explain state machine types. (10)
Q.10. Enumerate and explain loop statement. (10)

Group C : All Questions are Compulsory.
Q.11 Fill in the blanks (Each question carries 2 marks)
(i) Modules can have __________.
(ii) ____________ is the names you give your wires, gates, functions.
(iii) UDPS always have _________________ input.
(iv) Z mems _________________.
(v) String are stored in _________________.

Q.12 Multiple choice question. (Each question carries 2 marks)
(i) Every system has a delay before it is ________.
(a) Execution
(b) Run
(c) Compile
(d) Design

(ii) Output ports can have __________.
(a) Controls
(b) Registers
(c) Wires
(d) Modules

(iii) For sequential VDP, f stands for __________.
(a) Rising edge
(b) Falling edge
(c) Any change
(d) None of these

(iv) Take contains _________ statement.
(a) Single
(b) Double
(c) Triple
(d) None of these

(v) Function must take __________ time.
(a) One
(b) Two
(c) Zero
(d) Four

Q.13 True or false : (Each question carries 1 marks)
(i) Every wire and reg in verilog starts out unknown.
(ii) Parameters are run time constants.
(iii) Function must return the value.
(iv) Concentration can be used on one sides of an assignment.
(v) The wait statement if it is condition is true.

Digital VLSI Design :
Group A : Answer any three questions. (Question No. 1 is compulsory)
Q.1 Explain the CMOS lambda based design rules (05)
Q.2 Explain the BICMOS Inverter. (10)
Q.3. Draw and explain small signal model of MOS. (10)
Q.4. Explain two stage MOS operational amplifier design criteria (10)
Q.5. How analysis of differential amplifier can be done by using active load. (10)

Group B : Answer any three questions. (Question No. 6 is compulsory)
Q.6 Explain direct coupled FET logic inverter. (05)
Q.7 Explain carry slip adder. Give optimization of carry slip adder (10)
Q.8 Explain resistances and capacitances estimation. (10)
Q.9 What is n by m RAM using parameterized modules? Explain. (10)
Q.10 Design arithmetic logic unit. (10)

Group C : All Questions are Compulsory.
Q.11 Fill in the blanks (Each question carries 2 marks)
(i) Switch logic is based on_______ or trasmission gates.
(ii) As the separation between metal-semiconductor surface is reduced,the charge stored in the device _____.

(iii) Capture mode is used for ___________.
(iv) VCO is used for ________in communication field.
(v) Resolution of 8 bit A to D converter is ________.

Q.12 Multiple choice question : (Each question carries 2 marks)
(i) Which of the following processing techniques would be used to create the source and drain regions of a transistor?
(a) Oxidation
(b) Ion implantation
(c) Sputtering
(d) Polysilicon deposition

(ii) The capacitance of a transistor gate is proportional to what?
(a) The width of the gate
(b) The length of the gate
(c) The area of the gate
(d) The depth of the channel

(iii) Which addition is correct
(a) 0101+1111=11010
(b) 0101+1111=10100
(c) 0101+1111=11001

(iv) In N channel MOSFET with gate reverse biased, the gate current is of the order of
(a) 10¬-3amp
(b) 10-6amp
(c) 10-9 amp
(d) 10-12amp

(v) Given BCD 10010011,its decimal equivalent is
(a) 147
(b) 143
(c) 93
(d) 39

Q.13 True or false : (Each question carries 1 marks)
(i) The area capacitances are associated with layers to substrate & from gate to channel.
(ii) The ion implementation is achieved by bombarding high velocity electron on semiconductor surface.

(iii) CMOS logic family takes minimum power.
(iv) NOT gate cannot implemented by transistor.
(v) The meaning of decoder is many to one.