MCSCS105-3 Multicore Architecture M.Tech Model Question Paper : mgu.ac.in

Name of the College : Mahatma Gandhi University
Department : Computer Science and Engineering
Subject Code/Name : MCSCS 105-3/MULTICORE ARCHITECTURE
Sem : I
Website : mgu.ac.in
Document Type : Model Question Paper

Download Model/Sample Question Paper :
I : https://www.pdfquestion.in/uploads/mgu.ac.in/5015-1-MCSCS%20105-3%20Multicore%20Architecture%20set1(1).doc
II : https://www.pdfquestion.in/uploads/mgu.ac.in/5015-2-MCSCS%20105-3%20Multicore%20Architecture%20set2(1).doc

MGU Multicore Architecture Question Paper

M.TECH. DEGREE EXAMINATION :
Branch: Computer Science and Engineering
Specialization : Computer Science and Engineering

Related : MGU MCSCS105-2 Real Time Systems M.Tech Model Question Paper : www.pdfquestion.in/5014.html

Model Question Paper – I

First Semester :
MCSCS 105-3 MULTICORE ARCHITECTURE (Elective I)
(Regular – 2013 Admission onwards)
Time: 3hrs
Maximum:100 marks

Answer the following Questions :
1. a) What is Simultaneous Multithreading? (6)
b) Explain Dynamic Branch Prediction? (9)
c) Describe Superscalar processor Design?(10)
or

2. a) What is Hardware based Speculation? (8)
b) What is loop unrolling ? (8)
c) How data hazard are overcoming with dynamic scheduling? (9)

3. a) Explain relaxed consistency models for memory consistency? (7)
b) Explain how protection is provided in virtual memory? (7)
c) Describe eleven advanced optimizations for cache performance? (11)
or
4. a) Explain the issues related to Multicore caches? (9)
b) Describe distributed shared memory architecture? (6)
c) Explain protection in virtual memory and virtual machines? (10)

5. a) What is scalable cache coherence? (6)
b) How locks are implemented using coherence? (9)
c) Describe directory based cache coherence?(10)
or
6. a) Explain Split transaction bus with multilevel caches? (8)
b) Explain snoop based multiprocessor design? (8)
c) Describe the cache coherence protocols for single level caches and multilevel cache hierarchies? (9)

7. a) Explain PowerPC RISC Design? (8)
b) Describe arbitration logic? (7)
c) Give a description about Power 5 architecture? (10)
or
8. a) Explain Power processor element? (7)
b) Explain the router architecture in interconnection networks? (8)
c) Describe in detail the PowerPC architecture? (10)

Model Question Paper – II

MULTICORE ARCHITECTURE : (Elective I)
(Regular – 2013 Admission onwards)
Time: 3hrs
Maximum:100 marks
Answer the following Questions. :
1. a) Differentiate Hardware versus Software Speculation?(7)
b) Explain using of ILP to Exploit Thread Level Parallelism? (8)
c) Explain Dynamic Scheduling with Tomasulo Algorithm? (10)
or
2. a) Differentiate Multicore Versus Multithreading? (8)
b) How branch costs are reduced with Prediction? (8)
c) What are the limitations of ILP?(9)

3. a) Explain how protection is provided in virtual memory? (6)
b) Differentiate symmetric shared memory architecture and distributed shared memory architecture? (7)
c) Describe six basic cache optimization techniques? (12)
or
4. a) What are the techniques for fast address translation in virtual memory? (8)
b) What is symmetric shared memory architecture? Explain the performance of symmetric shared memory architecture? (8)
c) Describe the design of memory hierarchies? (9)

5. a) What is multiprocessor cache coherence problem? (8)
b) Describe multilevel cache hierarchies? (8)
c) Explain the synchronization mechanism for multiprocessors? (9)
or
6. a) What are the design challenges of directory based protocols? (8)
b) Explain Split transaction bus with multilevel caches? (8)
c) Describe snooping protocols with example protocols? (9)

7. a) Explain PowerPC Memory management system? (8)
b) Describe interconnection topologies? (7)
c) Give a description to Cell Broadband Engine? (10)
or
8. a) Explain Synergistic processing element? (7)
b) Explain the flow control mechanism in interconnection networks? (8)
c) Describe in detail the IBM Power 6 Architecture? (10)

Syllabus

Module 1 :
Fundamentals of Superscalar Processor Design- Limitations of ILP, Super Scalar Processor Design, Multi Threading, Thread Level Parallelism – Introduction to Multicore Architecture – Multicore Vs MultiThreading.

Module 2 :
Symmetric shared memory architectures, distributed shared memory architectures, Issues related to multicore caches, Design of mutlicore core caches, levels of caches, cache optimization, Models of memory consistency, Virtual Memory.

Module 3 :
Cache coherence protocols (MSI, MESI, MOESI),scalable cache coherence, Snoop-based Multiprocessor Design — Correctness requirements, design with single-level caches and an atomic bus, multilevel cache hierarchies, dealing with split-transaction bus, coherence for shared caches and virtually indexed caches, TLB coherence Overview of directory based approaches, design challenges of directory protocols, memory based directory protocols, cache based directory protocols, protocol design tradeoffs, synchronization.

Module 4 :
PowerPC architecture – RISC design, PowerPC ISA, PowerPC Memory Management Power 5 Multicore architecture design, Power 6 Architecture.

Cell Broad band engine architecture, PPE (Power Processor Element), SPE (Synergistic processing element) Interconnection Network Design – Interconnection topologies, routing techniques, flow control mechanisms, router architecture, arbitration logic.

References :
1. Hennessey & Paterson, “Computer Architecture A Quantitative Approach”, Harcourt Asia, Morgan Kaufmann, 1999.
2. Kai Hwang, “Advanced Computer Architecture: Parallelism, Scalability and
Programmability” McGraw-Hill,1993.