AN1625 ASIC Design M.E Question Bank : niceindia.com

Name of the College : Noorul Islam College of Engineering
University : Anna University
Degree : M.E
Department : Electrical & Electronics Engineering
Subject Code/Name : AN 1625 – ASIC Design
Document Type : Question Bank
Website : niceindia.com

Download Model/Sample Question Paper : https://www.pdfquestion.in/uploads/niceindia.com/3118-ASIC_DESIGN_-AN1625.pdf

NICE ASIC Design Question Bank

1.What is CMOS technology &write its advantages? :
1.combination of both NMOS and PMOS.
2.uses the polysilicon gate.

Related : Noorul Islam College of Engineering XSE471 Software Testing M.Sc Question Bank : www.pdfquestion.in/3128.html

Advantages :
1.Power consumption is less.

2.write the difference between custom ICand std IC? :
Std IC :
Directly got from the market RAM,ROM,DRAM>
Custom IC :
Meant for specific application lot of std.IC combined to form a custom IC.

3.Write the example of IC’s? :
** SRAM
** DRAM
** ROM

4.write some example of ASIC’s? :
** The chip inside the toy.
** Chip for a satellite.

5.What is mean by fullcustom ASIC’s? :
1.All the logic cells are customized.
2.All the mask layers that are customized.
3.Manufacturing is too difficult.

6.Write the different type of ASIC’s? :
1.Full custom ASIC.
2.Semicustom ASIC.
3.Programmable ASIC.

7.What is meant by CBIC? :
CBIC means Cell Based ASIC.
** All the Mos layers are customized.
** Custom blocks can be embedded.
** Manufacturing lead time about 8 weeks.

Ex :Flipflop,multiplexer,OR gate,AND gate.

8.Write the important features of CBIC? :
** Designers can save money and time is reduced by using predesigned,pretested and precharacteristic.
** Logic cells can be optimized individually.
** Transistors are choosen to maximize or minimize the speed.

9.Define the term feedthrough? :
The term feedthrough can refer either to the piece of metal that is used to pass a signal through a cell or to a space in a cell waiting to be used as a feedthrough.

10.What is mean bygate array based IC and write its type? :
** The transistors are predefined on the silicon wafer.
** Predefined transistors on the gate array is known as base array.
** The smallest element that can be replicated to form the base array is called base cells.
** Number of layers .
** Bottom layers consists of transistors.

Type :
** Channeled gate array
** Channeless gate array
** Structured gate array

11.What are the important parts in the datapath library? :
A datapath library typically contains cells such as adders,subtracters,multipliers& simple Arithmetic And Logical Units.

12.Define structure gate array? :
** Only the interconnections are customized.
** custom blocks can be embedded.
** Manufacturing lead time is between two days and two weeks.

13.What is difference between channeled and channeless gate array? :
Channeless gate array :
** No predefined areas between row and std cells.
** Logic density of the channeless gate array is high
** Contact mask is customized in the channeless gate array.

Channeled gate array :
** Predefined areas between row and std cells.
** Logic density of the channeless gate array is low.
** Contact mask is not customized in the channeless gate array

14.Write the design flow of an ASIC? :

15.Define the transit time? :
Time is taken by electron travel from source to drain.This is called as the transit time.

16. What is meant by derating factor?
To convert nominal or typical timing figures to worst case timing figures we use measured or empirically derived constants called derating factors.

17. Define critical path
Minimum delay path between the registers is called critical path.

18. Define worst case timing
Designers thus need to know the maximum delays they may encounter, which we call the worst case timing.

19.What is meant by speed grading
*Most of the FPGA header short chip according to speed is called speed binning or speed grading.

20.Define a. Logic expander
b.Programmable inversion
Logic expander
*The logic expander to generate extra
logic terms, it possible to implement
function that require more product term
that are available in the simple PAL
macrocell.

21. Define channel density?
It is the absolute minimum number of tracks needed in a channel to make a given set of connections.

22. What is meant by PIPs?
The Programmable Interconnect Points (PIPs) are Programmable pass transistors that connect the CLB inputs and outputs to the routing network.

23. What is meant by BIDA?
The Bidirectional Interconnect Buffers(BIDA) restore the logic level and logic strength on long interconnect paths.

24. Write some points about Xilinx EPLD architecture?
This family uses an interconnect bus known as Universal Interconnection Module
(UIM) to distribute signals within the FPGA.
• CG is the fixed gate capacitance of the EPROM device.
• CD is the fixed drain parasitic capacitance of the EPROM device.
• Cw is the variable vertical bus capacitance.

25. Define OEM?
For any ASIC, a designer needs design-entry software, a cell library and
physical design software. Often designers buy that software from FPGA vendor. This is
called an Orginal Equipment Manufacturer (OEM) arrangement.