CPLD & FPGA Architectures & Applications M.Tech Question Paper : vardhaman.org

College : Vardhaman College Of Engineering
Degree : M.Tech
Semester : I
Department : Digital Electronics and Communication Systems
Subject :CPLD & FPGA Architectures & Applications
Document type : Question Paper
Website : vardhaman.org

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Vardhaman CPLD & FPGA Question Paper

(Regulations: VCE-R11)
(Digital Electronics and Communication Systems)
Date : 14 February, 2014
Time : 3 Hours
Max. Marks : 60

Related : Vardhaman College Of Engineering Adavanced Data Communications M.Tech Question Paper : www.pdfquestion.in/6419.html

February 2014

Answer any FIVE Questions.
All Questions carry equal marks

1. a) With a flow chart, explain the design abstractions for FPGA’s. 6M
b) Explain the following with respect to FPGA based system design:
i. Performance
ii. Power
iii. Design time 6M

2. a) With a neat block diagram, explain the generic structure of FPGA Fabric. 6M
b) With a neat block diagram, explain the XILINX SPARTAN II combinational logic block. 6M

3. a) With a neat block diagram, explain the ALTERA APEX II I/O Pin. 8M
b) Explain the logic element cluster. 4M
4. a) With a neat block diagram, explain the operation of carry select adder. 8M
b) Explain how unnecessary glitch propagation can be eliminated in FPGA base systems. 4M

5. Explain the following:
i. Syntax directed translation
ii. Logic synthesis
iii. Logic implementation by macro 12M

6. a) Write the verilog code to detect the sequence “110”. 8M
b) Explain the Register Transfer Structure. 4M

7. a) Explain PAL output with programmable polarity. 6M
b) Explain the generic block diagram of complex PLD. 6M
8. a) Explain programmable routing matrix of xilinx 4000 series. 6M
b) How sequential circuit is implemented in ALTERA’S FLEX 8000 series? 6M

July 2014

CPLD AND FPGA ARCHITECTURES AND APPLICATIONS
(Digital Electronics and Communication Systems)
Date: 26 July, 2014
Time: 3 hours
Max Marks: 60
Answer any Five Questions.
All Questions carry equal marks.

All parts of the question must be answered in one place only.

1. a) Explain advantages, history of FPGA and also discuss FPGA based system design briefly. 6M
b) With neat flowchart, explain design abstraction ladder for FPGAs. 6M
2. a) With a neat block diagram, explain the operation of ALTERA APEX II logic element. 8M
b) Explain permanently programmed FPGA’s. 4M
3. a) Discuss the different logic elements to design FPGAs fabrics. 6M
b) How will you connect two logic elements in FPGA? Illustrate Rents rule. 6M

4. Explain the following:
i. Gate and wire delay
ii. Static timing analysis
iii. Critical path 12M

5. a) Explain:
i. Technology independent logic optimization
ii. Technology dependent logic optimization 8M

b) Draw the schematics that represent the results of syntax directed translation of these statements:
i. if (e) then x<=a|b;
else x<=a&~b;
ii. if (e) then x<=a;
else x<=a&~b; 4M

6. Design a mealy FSM for a sequence detector which detects “001”.The FSM output is ‘1’ if the sequence is detected otherwise ‘0’. Write the verilog code for the same. 12M
7. a) Design a BCD Counter using appropriate programmable logic element or device. 6M
b) Explain in detail about programmable sum -of -products array. 6M
8. a) Draw the simplified block diagram of Xilinx XC4000 series CLB and explain the function briefly. 6M
b) Compare & list out the advantages of ALTERAs logic8000 with Xilinx XC4000. 6M

CPLD AND FPGA Architectures And Applications :
(Digital Electronics and Communication Systems)
Time: 3 hours
Max Marks: 60
Answer any FIVE Questions.
All Questions carry equal marks

All parts of the questions must be answered in one place only :
1. a) Explain advantages and history of FPGA. 6M
b) With neat flowchart, explain design abstraction ladder for FPGAs. 6M
2. a) Describe Xilinx Spartan-II combinational logic block with neat logic diagram. 6M
b) Explain one time programmable based FPGA. Write its basic programming elements. 6M

3. a) Discuss the different logic elements to design FPGAs fabrics. 6M
b) How will you connect two logic elements in FPGA? Illustrate Rents rule. 6M
4. a) Why power and energy optimization is required for logic circuit? Explain. 6M
b) What is barrel shifter & serial adder? Write their importance with block view. 6M

5. a) Explain syntax directed translation with example. How you will implement the logic by macro. 6M
b) Describe the importance of placement in FPGA. Differentiate Clustering Vs Partitioning.6M
6. a) Explain the sequential machine design process by taking suitable example. 6M
b) Discuss the clocking disciplines. 6M

7. a) Describe PAL outputs with programmable polarity. 6M
b) Design BCD counter using appropriate programmable logic elements or devices. 6M
8. a) Draw the simplified block diagram for Xilinx XC4000 series CLB and explain the function briefly. 6M
b) Compare & list out the advantages of ALTERAs logic8000 with Xilinx XC4000. 6M