Mathematics For Aerospace Engineers B.Tech Question Paper : vardhaman.org
College : Vardhaman College Of Engineering
Degree : B.Tech
Department : Aeronautical Engineering
Semester : III
Subject :Mathematics For Aerospace Engineers
Document type : Question Paper
Website : vardhaman.org
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Mathematics For Aerospace Engineers Question Paper :
B. Tech III Semester Regular Examinations, December – 2013
(Regulations : VCE-R11)
(Aeronautical Engineering)
Date : 2 December, 2013
Time : 3 Hours
Max. Marks : 75
Related : Vardhaman College Of Engineering Machine Drawing B.Tech Question Paper : www.pdfquestion.in/6303.html
Answer ONE question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
Unit – 1 :
1. a) Express x x dx m n p (1 ) 10? in terms of the beta function and evaluate x x dx 7M
b) Prove that 2 sin cos 1 22m n 8M
2. a) Prove that ( ) ( ) 0 1 0 ? xJ x J x dx ? n n ? ? Where ? and ? are distinct roots of J (x) ? 0.
b) Prove that ( 1) ( ) (2 1) ( ) ( ). 1 1 n P x n xP x nP x n? n n? ? ? ? ? 7M
Unit – 2 :
3. a) For a certain two –dimensional flow, the stream function is – 2 2 y x y 7M
(x, y) ? (0,0). Find the velocity potential. 7M
b) Find the constant ‘a’ such that u = cos ax coshy is Harmonic. Also write down f(z) 8M
4. a) Determine all the values of (1 ) . 8M
Unit – 3 :
5. a) Verify Cauchy’s theorem for the integral of 3 z taken over the boundary of the rectangle with vertices ?1, 1, 1?i, ?1?i 8M
b) Evaluate 1 2 0 ( ) i x iy dz ? along the path y ? x. 7M
Unit – 5 :
9. a) Determine the region of the w – plane into which the following regions are mapped by the transformation 2w ? z .
i. Region bounded by the first quadrant of z – plane.
ii. Region bounded by x ?1, y ?1, x ? y ?1. 8M
b) Find the bilinear transformation which maps the points z ?1,?i,?1 into the points w ? i,0,?i 7M
10. a) Discuss the transformation w=e
Digital Logic Design :
(Common to Computer Science and Engineering, Information Technology,
Electronics and Communication Engineering & Electrical and Electronics Engineering)
Date : 6 December, 2013
Time : 3 Hours
Max. Marks : 75
Answer ONE question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
Unit – 1 :
1. a) Perform the following operations indicating the complete procedure:
i. 2 10 (?) ? (53.6875)
ii. 10 2 (?) ? (11111111.1011)
iii. 2 8 (?) ? (265.354)
iv. 8 2 (?) ? (010110101.011101100) 8M
b) Find minimal SOP expression of the Boolean function Y(a,b,c,d) = abc + abd + a’bc’ + cd + bd’
2. a) Perform the following arithmetic using 2’s complement method. 6M
i. + 6 + 9 =
ii. – 6 + 9 =
iii. + 6 – 9 =
b) Minimize the logic expression below and draw the logic circuit for the simplified expressions.Y ? ABC ? ABC ? ABC 6M
c) With examples explain the methods of signed binary numbers representation. 3M
Unit – 2 :
3. a) Using Quine-McLuskey method, determine the minimal sum for the Boolean function: f (w, x, y, z) ??m(1, 4, 6, 7, 8, 9,10,11,15) 10M
b) Realize the function: f (w, x, y, z) ??m(0,1, 5, 6, 7, 9,12,15) using a 4:1 MUX and external gates, considering w and z as select lines.5M
4. a) Simplify the logic function given below, using Map entered variable technique, considering ‘ z ’ as the map entered variable: f (w, x, y, z) ??m(2, 3, 4, 5,13,15) ? d(8, 9,10,11) 10M
b) Find all the prime implicants of the following function using K-map: f (w, x, y, z) ??m(3, 4, 5, 7,10,12,14,15) ? d(2)
Unit – 3 :
5. a) Design a synchronous mod-6, counter with the following sequence: 5, 6, 7, 8, 9, 10, 5…… 10M
b) Convert SR flip-flop to JK flip-flop. 5M
6. a) Briefly explain the ‘race around’ condition in a flip-flop. What are the ways of eliminating this condition? Explain any one in detail 10M
b) Design a 4-bit Binary ripple down-counter using a negative edge triggered D flip-flops 5M
Unit – 4 :
7. a) Design a combinational circuit using ROM that accepts a three bit binary number and produces its square at the output. 8M
b) Implement the multi-output function given using PLA. F1 = AB’ + AC + A’BC’; F2 = (AC + BC)’ 7M
8. a) What are the different Programmable Logic Devices used for digital system implementations? Explain them briefly. 7M
b) A multi-output function is defined by the switching functions; 1 2 F ??m(0,1, 2, 4), F ??m(0, 5, 6, 7) and 3 F ??m(0, 3, 5, 7) . Prepare a PLA programming table for implementation. 8M
Unit – 5 :
9. a) Explain the basic elements in ASM chart. 7M
b) Draw the state diagram, state table and ASM chart for the JK flip-flop. 8M
10. a) Explain the determination of state equivalence using implication table with an example. 8M
b) What is an ASM chart? Explain the difference between state diagram and ASM chart with an example. 7M